Integrated circuits are widely used in consumer, commercial and industrial applications. As is well known to those having skill in the art, an integrated circuit may comprise an integrated circuit substrate, such as a silicon semiconductor substrate including a plurality of a microelectronic devices therein, and an interconnect system on the integrated circuit substrate for selectively interconnecting the microelectronic devices and/or for providing power supply and/or input/output connections. As the integration density of integrated circuit devices continues to increase, it may be difficult to form interconnections among these high density microelectronic devices with sufficient quality and/or reliability.
Copper is being investigated and used as a high quality and/or high reliability interconnect metal for high density integrated circuits. Copper-based interconnect systems may replace aluminum, tungsten via/aluminum-copper wire, and/or other integrated circuit interconnect systems.
One method for fabricating copper interconnects is referred to as a “damascene” or “dual-damascene” method. In a damascene method, an underlying conductive layer is covered with a dielectric or insulator, such as silicon dioxide. A patterned photoresist profile is then formed over the dielectric, and an interconnection trench or groove is etched into the dielectric. Another layer of resist has an opening or hole overlying the trench, corresponding to the area in the dielectric where a via is to be formed. The dielectric not covered with the photoresist is then etched to remove oxide underlying the hole in the photoresist to create vias in the dielectric. The photoresist is then stripped away. A thin film of copper, or some other metallic material, then is used to fill the via and trench. The excess copper remaining is removed, for example using Chemical Mechanical Polishing (CMP). The result is an inlaid or damascene structure in the dielectric layer. See U.S. Pat. No. 6,023,102 to Nguyen et al., entitled Low Resistance Contact Between Circuit Metal Levels, Column 2, lines 27–46. Other copper damascene structures and fabrication processes are described in U.S. Pat. No. 5,989,623 to Chen et al., entitled Dual Damascene Metallization; U.S. Pat. No. 6,114,243 to Gupta et al., entitled Method to Avoid Copper Contamination on the Sidewall of a Via or a Dual Damascene Structure; U.S. Pat. No. 6,207,222 to Chen et al., entitled Dual Damascene Metallization; U.S. Pat. No. 6,218,303 to Lin entitled Via Formation Using Oxide Reduction of Underlying Copper; and U.S. Pat. No. 6,350,688 to Liu et al., entitled Via RC Improvement for Copper Damascene and Beyond Technology.
It is well known that electromigration can impact the reliability of metal-based interconnects for integrated circuits. As is well known to those having skill in the art, electromigration is the motion of ions of a conductor, such as aluminum or copper, in response to the passage of current through it. A divergence of ionic flux can lead to an accumulation of vacancies or voids in the conductor. These voids may grow to be a large enough size so as to cause an open circuit failure of the conductor.
Electromigration has been studied in copper interconnects. See, for example, the publication by Hu et al., Copper Interconnections and Reliability, Materials Chemistry and Physics, Vol. 52, 1998, pp. 5–16; Hu et al., Electromigration in 0.25 μm Wide Cu Line on W, Thin Solid Films, Vol. 308–309, 1997, pp. 443–447 and by Ogawa et al., Electromigration Reliability of Dual-Damascene Cu/Oxide Interconnects, Materials Research Society Symposia Proceedings, Vol. 612, 2000, pp. D2.3.1–D.2.3.6.
Statistical studies have revealed multi-mode failures in copper-based dual-damascene structures, one mode of failure due to void formation at the via interface and other modes comprising void formation in the line or metal extrusion near the end of the metal line. Void formation at the via interface usually occurs faster than other failure modes, therefore it dominates the early failures of copper interconnects. See, for example, the publication by Gall et al., Statistical Analysis of Early Failures in Electromigration, Journal of Applied Physics, Vol. 90, 2001, p. 732–740; Ogawa et al., Statistics of Electromigration Early Failures in Cu/Oxide Dual-Damascene Interconnects, 2001 IEEE International Reliability Physics Symposium Proceedings, 39th Annual, 2001, pp. 341–349; and Lee et al., Statistical Study of Electromigration Early Failures in Dual-Damascene Cu/Oxide Interconnects, AIP Conference Proceedings on Stress Induced Phenomena in Metallization: Sixth International Workshop, 2001, pp. 61–73. Early failures may be a significant concern, since they may dominate the lifetime of the integrated circuit as the device scaling results in increasing interconnect density. Electromigration failure at the via may be caused by flux divergence occurring at the via/line interface due to the presence of a diffusion barrier and due to the via geometry.
Attempts have been made to improve the electromigration resistance of copper-based interconnects. One attempt is described in Ueno et al., A High Reliability Copper Dual-Damascene Interconnection With Direct-Contact Via Structure, AIP Conference Proceedings on Stress Induced Phenomena in Metallization: Sixth International Workshop, 2001, pp. 49–60. As described therein, a new via technology for improving electromigration (EM) reliability of copper (Cu) dual-damascene (DD) interconnection has been developed. Early failure mode of a conventional Cu DD structure is found as void formation at the via-bottom interface, where flux divergence of Cu ions is large due to diffusion barrier layer. In order to avoid the early failures, direct-contact via (DCV) technology whose concept is “barrier-free” at the via-bottom has been developed. The early failure mode is eliminated by the DCV technology and lower via resistance is obtained.
Another attempt at improving the electromigration reliability of copper-based interconnects is described in U.S. Pat. No. 6,306,732 to Brown, entitled Method and Apparatus for Simultaneously Improving the Electromigration Reliability and Resistance of Damascene Vias Using A Controlled Diffusivity Barrier. As described therein, an apparatus for improving electromigration reliability and resistance of a single- or dual-damascene via includes an imperfect barrier formed at the bottom of the via, and a stronger barrier formed at all other portions of the via. The imperfect barrier allows for metal atoms, such as copper atoms, to flow therethrough when the electromigration force pushes the metal atoms against the barrier. That way, the metal atoms that are pushed away from the downstream side of the barrier are replaced by metal atoms that flow through the barrier from the upstream side of the barrier. The imperfect barrier may be formed by biasing a wafer, and having the atoms resputter from the bottom of the via and adhere to the sidewalls of the via. The imperfect barrier may also be formed by a two-layered barrier, where a first layer corresponds to a good step coverage, poor barrier, and where the second barrier corresponds to a poor step coverage, good barrier. The imperfect barrier may also be formed by depositing the barrier conformally, and providing a directional etch to the portions of the barrier that are deposited to the bottom of the via. See the Brown Abstract.